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| author |   Claudiu Beznea <claudiu.beznea@microchip.com> | 2021-04-15 13:50:02 +0300 |
|---|---|---|
| committer |   Nicolas Ferre <nicolas.ferre@microchip.com> | 2021-07-19 15:27:14 +0200 |
| commit | b6862714078c5259ba5eb4785c8575d876bc7bf5 (patch) | |
| tree | a9df3b0c2da1ddfed20cc387c37a9e1562cbe585 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek (diff) | |
| download | wireguard-linux-b6862714078c5259ba5eb4785c8575d876bc7bf5.tar.xz wireguard-linux-b6862714078c5259ba5eb4785c8575d876bc7bf5.zip | |
dt-bindings: atmel-sysreg: add bindings for sama7g5
Add RAM controller and RAM PHY controller DT bindings.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20210415105010.569620-17-claudiu.beznea@microchip.com
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
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