diff options
| author |   Russell King (Oracle) <rmk+kernel@armlinux.org.uk> | 2025-04-12 09:08:29 +0100 |
|---|---|---|
| committer |   Jakub Kicinski <kuba@kernel.org> | 2025-04-14 17:12:40 -0700 |
| commit | dadc3a6be46987d9417732e5b59476267bba76ed (patch) | |
| tree | c6aa7a93b52f2ffd06aca3a8cf1cf9a128fc12c5 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | Merge branch 'net-convert-exit_batch_rtnl-to-exit_rtnl' (diff) | |
| download | wireguard-linux-dadc3a6be46987d9417732e5b59476267bba76ed.tar.xz wireguard-linux-dadc3a6be46987d9417732e5b59476267bba76ed.zip | |
net: stmmac: dwc-qos: remove tegra_eqos_init()
tegra_eqos_init() initialises the 1US TIC counter for the EEE timers.
However, the DWGMAC core is reset after this write, which clears
this register to its default.
However, dwmac4_core_init() configures this register using the same
clock, which happens after reset - thus this is the write which
ensures that the register is correctly configured.
Therefore, tegra_eqos_init() is not required and is removed. This also
means eqos->clk_slave can also be removed.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Link: https://patch.msgid.link/E1u3Vuf-000E7g-U4@rmk-PC.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions