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| author |   Phil Edworthy <phil.edworthy@renesas.com> | 2022-05-18 14:52:08 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2022-06-06 11:13:30 +0200 |
| commit | e55c4481e71de79d0ef566a238332bd346cef6de (patch) | |
| tree | 2faa4be3751bfae367312fa79663d467de12a834 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | clk: renesas: r9a07g044: Add POEG clock and reset entries (diff) | |
| download | wireguard-linux-e55c4481e71de79d0ef566a238332bd346cef6de.tar.xz wireguard-linux-e55c4481e71de79d0ef566a238332bd346cef6de.zip | |
clk: renesas: r9a09g011: Add PFC clock and reset entries
Add PFC clock/reset entries to CPG driver.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220518135208.39885-1-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions