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| author |   Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2023-07-07 22:39:32 +0300 |
|---|---|---|
| committer |   Abhinav Kumar <quic_abhinavk@quicinc.com> | 2023-07-13 11:56:24 -0700 |
| commit | e8383f5cf1b3573ce140a80bfbfd809278ab16d6 (patch) | |
| tree | 4383ddb430f1cef794e5e912a74b4072353d1bd0 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | drm/msm/dpu: add missing flush and fetch bits for DMA4/DMA5 planes (diff) | |
| download | wireguard-linux-e8383f5cf1b3573ce140a80bfbfd809278ab16d6.tar.xz wireguard-linux-e8383f5cf1b3573ce140a80bfbfd809278ab16d6.zip | |
drm/msm/dpu: drop enum dpu_core_perf_data_bus_id
Drop the leftover of bus-client -> interconnect conversion, the enum
dpu_core_perf_data_bus_id.
Fixes: cb88482e2570 ("drm/msm/dpu: clean up references of DPU custom bus scaling")
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/546048/
Link: https://lore.kernel.org/r/20230707193942.3806526-2-dmitry.baryshkov@linaro.org
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions