diff options
| author |   Julien Grall <julien.grall@arm.com> | 2019-10-14 11:21:13 +0100 |
|---|---|---|
| committer |   Will Deacon <will@kernel.org> | 2019-10-14 17:56:57 -0700 |
| commit | ec52c7134b1fcef0edfc56d55072fd4f261ef198 (patch) | |
| tree | d5c3cffad34849de6ff23ff92dd53ed3386093f6 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | arm64: Fix kcore macros after 52-bit virtual addressing fallout (diff) | |
| download | wireguard-linux-ec52c7134b1fcef0edfc56d55072fd4f261ef198.tar.xz wireguard-linux-ec52c7134b1fcef0edfc56d55072fd4f261ef198.zip | |
arm64: cpufeature: Treat ID_AA64ZFR0_EL1 as RAZ when SVE is not enabled
If CONFIG_ARM64_SVE=n then we fail to report ID_AA64ZFR0_EL1 as 0 when
read by userspace, despite being required by the architecture. Although
this is theoretically a change in ABI, userspace will first check for
the presence of SVE via the HWCAP or the ID_AA64PFR0_EL1.SVE field
before probing the ID_AA64ZFR0_EL1 register. Given that these are
reported correctly for this configuration, we can safely tighten up the
current behaviour.
Ensure ID_AA64ZFR0_EL1 is treated as RAZ when CONFIG_ARM64_SVE=n.
Signed-off-by: Julien Grall <julien.grall@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Dave Martin <dave.martin@arm.com>
Fixes: 06a916feca2b ("arm64: Expose SVE2 features for userspace")
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions