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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2022-10-12 16:03:44 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-10-26 12:38:01 +0200 |
| commit | ed823991c6ecfb04f6511337fd2086257d08fac8 (patch) | |
| tree | 6c68a7c972416ed19913dd0a8f99565aa2aaa2cb /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | clk: renesas: r8a779g0: Add SDHI clocks (diff) | |
| download | wireguard-linux-ed823991c6ecfb04f6511337fd2086257d08fac8.tar.xz wireguard-linux-ed823991c6ecfb04f6511337fd2086257d08fac8.zip | |
clk: renesas: r8a779g0: Add RPC-IF clock
Add the module clock used by the SPI Multi I/O Bus Controller (RPC-IF)
on the Renesas R-Car V4H (R8A779G0) SoC.
While at it, fix table alignment in the definition of the related
RPCSRC internal clock.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/f0609c82e742865be753b67a0a6080f193f405ad.1665583328.git.geert+renesas@glider.be
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions