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| author |   Cong Dang <cong.dang.xn@renesas.com> | 2024-01-26 11:44:05 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2024-02-20 11:43:48 +0100 |
| commit | fbaff0364a42e3160c0fbc56087c4348434066d1 (patch) | |
| tree | 25155b975fc954ae85b1c451e037e25723ce0645 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | pinctrl: renesas: r8a779h0: Add SCIF pins, groups, functions (diff) | |
| download | wireguard-linux-fbaff0364a42e3160c0fbc56087c4348434066d1.tar.xz wireguard-linux-fbaff0364a42e3160c0fbc56087c4348434066d1.zip | |
pinctrl: renesas: r8a779h0: Add SCIF_CLK pins, groups, functions
Add pins, groups and functions for the baud rate generation clock pins
(SCIF_CLK) on the Renesas R-Car V4M (R8A779H0) SoC.
Signed-off-by: Cong Dang <cong.dang.xn@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/ee056d78d3a339bdbcca2cc5281f1fe01bbc3953.1706264667.git.geert+renesas@glider.be
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions