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| author |   Andrew F. Davis <afd@ti.com> | 2017-12-12 16:43:06 -0600 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2017-12-13 12:27:48 +0000 |
| commit | 77bdb58795d86262e96ba37524489ba0969de253 (patch) | |
| tree | fb0c1a58198d843ffeb98ededc381a969819889f /tools/perf/scripts/python/failed-syscalls-by-pid.py | |
| parent | ASoC: tlv320aic32x4: Use correct shift definition for DATATYPE bits (diff) | |
| download | wireguard-linux-77bdb58795d86262e96ba37524489ba0969de253.tar.xz wireguard-linux-77bdb58795d86262e96ba37524489ba0969de253.zip | |
ASoC: tlv320aic32x4: Use correct shift definition for DATALEN bits
Setting the DATALEN bit field requires shifting our value by 4. Setting
the OSR value of the PLL divider also requires a shift by 4. Currently
the code abuses this fact and uses the shift for the divider register to
set the data-length register. Fix this here by using the definition meant
for this register.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/failed-syscalls-by-pid.py')
0 files changed, 0 insertions, 0 deletions