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| author |   David Kaplan <david.kaplan@amd.com> | 2025-06-25 10:58:03 -0500 |
|---|---|---|
| committer |   Ingo Molnar <mingo@kernel.org> | 2025-06-26 10:56:39 +0200 |
| commit | 1fd5eb02867ac7db9144bd44c8edfad0189c8e57 (patch) | |
| tree | 68efa5768c00e158118273022ea43888602a2303 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | x86/bugs: Allow ITS stuffing in eIBRS+retpoline mode also (diff) | |
| download | wireguard-linux-1fd5eb02867ac7db9144bd44c8edfad0189c8e57.tar.xz wireguard-linux-1fd5eb02867ac7db9144bd44c8edfad0189c8e57.zip | |
x86/bugs: Add SRSO_MITIGATION_NOSMT
AMD Zen1 and Zen2 CPUs with SMT disabled are not vulnerable to SRSO.
Instead of overloading the X86_FEATURE_SRSO_NO bit to indicate this,
define a separate mitigation to make the code cleaner.
Signed-off-by: David Kaplan <david.kaplan@amd.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Reviewed-by: Borislav Petkov (AMD) <bp@alien8.de>
Cc: H . Peter Anvin <hpa@zytor.com>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Josh Poimboeuf <jpoimboe@kernel.org>
Cc: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: https://lore.kernel.org/r/20250625155805.600376-2-david.kaplan@amd.com
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions