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| author |   Paweł Anikiel <pan@semihalf.com> | 2023-04-14 16:02:00 +0200 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2023-04-17 12:55:55 +0100 |
| commit | 8076c586bbc1c62e075e58f41dafdd8b5022b24d (patch) | |
| tree | bb0da1ad3bb43e64e3ef7ea916dee227d6f2de58 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | ASoC: nau8825: Add delay control for input path (diff) | |
| download | wireguard-linux-8076c586bbc1c62e075e58f41dafdd8b5022b24d.tar.xz wireguard-linux-8076c586bbc1c62e075e58f41dafdd8b5022b24d.zip | |
ASoC: ssm2602: Add support for CLKDIV2
The SSM260x chips have an internal MCLK /2 divider (bit D7 in register
R8). Add logic that allows for more MCLK values using this divider.
Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Link: https://lore.kernel.org/r/20230414140203.707729-7-pan@semihalf.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions