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| author |   Paulo Zanoni <paulo.r.zanoni@intel.com> | 2018-06-14 15:10:17 -0700 |
|---|---|---|
| committer | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2018-06-15 15:06:00 -0700 |
| commit | 9378985eb05c486b32a61b69945df3297c6e854d (patch) | |
| tree | d45cdc90be600dcbc6f8adb6e612c7fd807b9224 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | drm/i915: s/IS_G4X && !IS_GM45/IS_G45/ (diff) | |
| download | wireguard-linux-9378985eb05c486b32a61b69945df3297c6e854d.tar.xz wireguard-linux-9378985eb05c486b32a61b69945df3297c6e854d.zip | |
drm/i915/icl: implement DVFS for ICL
ICL DVFS is almost the same as CNL, except for the CDCLK/DDICLK
table. Implement it just like CNL does.
References: commit 48469eced282 ("drm/i915: Use cdclk_state->voltage
on CNL")
References: commit 53e9bf5e8159 ("drm/i915: Adjust system agent
voltage on CNL if required by DDI ports")
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180614221018.19044-1-paulo.r.zanoni@intel.com
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions