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| author |   Ville Syrjälä <ville.syrjala@linux.intel.com> | 2016-05-13 23:41:32 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2016-05-23 21:11:15 +0300 |
| commit | 63911d7295524e59205ecfa3b2db437544c52eb8 (patch) | |
| tree | 8c5af3fbd12fe94cc551f9ea1d7257a73d4617f6 /tools/perf/scripts/python/sched-migration.py | |
| parent | drm/i915: Make 308 and 671 MHz cdclks more accurate on SKL (diff) | |
| download | wireguard-linux-63911d7295524e59205ecfa3b2db437544c52eb8.tar.xz wireguard-linux-63911d7295524e59205ecfa3b2db437544c52eb8.zip | |
drm/i915: Rename skl_vco_freq to cdclk_pll.vco
We'll want to store the cdclk PLL (whatever PLL that is in reality) vco
frequency somewhere on other platforms too, so let's rename the
skl_vco_freq to cdclk_pll.vco, and let's store it in kHz instead of MHz
to match most of the other clocks.
v2: Drop the spurious > vs != change (Imre)
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1463172100-24715-14-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Imre Deak <imre.deak@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/sched-migration.py')
0 files changed, 0 insertions, 0 deletions