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| author |   Zhenyu Wang <zhenyuw@linux.intel.com> | 2018-02-22 15:16:13 +0800 |
|---|---|---|
| committer | Zhenyu Wang <zhenyuw@linux.intel.com> | 2018-03-06 13:19:24 +0800 |
| commit | 9803984581de2b09290338687a3d21a7cd16685b (patch) | |
| tree | 16886bf4286f4c8bb095d1b1472d1f22849238f5 /tools/perf/scripts/python/sched-migration.py | |
| parent | drm/i915/gvt: remove gvt max port definition (diff) | |
| download | wireguard-linux-9803984581de2b09290338687a3d21a7cd16685b.tar.xz wireguard-linux-9803984581de2b09290338687a3d21a7cd16685b.zip | |
drm/i915/gvt: Fix vGPU sched timeslice calculation warning
Fix below warning by using proper ktime helper to calculate timeslice.
CHECK drivers/gpu/drm/i915//gvt/sched_policy.c
drivers/gpu/drm/i915//gvt/sched_policy.c:108 gvt_balance_timeslice() debug: sval_binop_signed: invalid divide LLONG_MIN/-1
drivers/gpu/drm/i915//gvt/sched_policy.c:108 gvt_balance_timeslice() debug: sval_binop_signed: invalid divide LLONG_MIN/-1
Reviewed-by: Zhi Wang <zhi.a.wang@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Diffstat (limited to 'tools/perf/scripts/python/sched-migration.py')
0 files changed, 0 insertions, 0 deletions