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| author |   Will Deacon <will.deacon@arm.com> | 2010-09-14 09:51:43 +0100 |
|---|---|---|
| committer |   Russell King <rmk+kernel@arm.linux.org.uk> | 2010-09-17 10:16:51 +0100 |
| commit | 9f05027c7cb3cfe56a31892bd83391138d41a667 (patch) | |
| tree | efe9361be8e1b8d78ff44ef13a1e46e1a4b9b23a /tools/perf/scripts/python/sctop.py | |
| parent | ARM: 6387/1: errata: check primary part ID in proc-v7.S (diff) | |
| download | wireguard-linux-9f05027c7cb3cfe56a31892bd83391138d41a667.tar.xz wireguard-linux-9f05027c7cb3cfe56a31892bd83391138d41a667.zip | |
ARM: 6388/1: errata: DMB operation may be faulty
On versions of the Cortex-A9 up to and including r2p2, under rare
circumstances, a DMB instruction between 2 write operations may not
ensure the correct visibility ordering of the 2 writes.
This workaround sets a bit in the diagnostic register of the Cortex-A9,
causing the DMB instruction to behave like a DSB, which functions
correctly on the affected cores.
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'tools/perf/scripts/python/sctop.py')
0 files changed, 0 insertions, 0 deletions