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| author |   Minda Chen <minda.chen@starfivetech.com> | 2023-06-29 15:51:11 +0800 |
|---|---|---|
| committer |   Vinod Koul <vkoul@kernel.org> | 2023-07-12 22:27:44 +0530 |
| commit | 2689c9c4ab6006342fce9dd88a0d63a24cf9c05f (patch) | |
| tree | 6a18c5ee10b814767663d6a6fabd7404d345577b /tools/perf/scripts/python/stackcollapse.py | |
| parent | phy: cadence: Sierra: Add single link SGMII register configuration (diff) | |
| download | wireguard-linux-2689c9c4ab6006342fce9dd88a0d63a24cf9c05f.tar.xz wireguard-linux-2689c9c4ab6006342fce9dd88a0d63a24cf9c05f.zip | |
dt-bindings: phy: Add StarFive JH7110 USB PHY
Add StarFive JH7110 SoC USB 2.0 PHY dt-binding.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230629075115.11934-2-minda.chen@starfivetech.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions