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| author |   Remi Pommarel <repk@triplefau.lt> | 2020-03-09 22:01:56 +0100 |
|---|---|---|
| committer |   Jerome Brunet <jbrunet@baylibre.com> | 2021-02-09 13:32:59 +0100 |
| commit | 31035839540e3f1669f9e47222108e9278651943 (patch) | |
| tree | de1c67050817de94ecabd93b954882423850aee5 /tools/perf/scripts/python/stackcollapse.py | |
| parent | clk: meson-axg: remove CLKID_MIPI_ENABLE (diff) | |
| download | wireguard-linux-31035839540e3f1669f9e47222108e9278651943.tar.xz wireguard-linux-31035839540e3f1669f9e47222108e9278651943.zip | |
clk: meson: axg: Remove MIPI enable clock gate
On AXG platforms HHI_MIPI_CNTL0 is part of the MIPI/PCIe analog PHY
region and is not related to clock one and can be removed from it.
Signed-off-by: Remi Pommarel <repk@triplefau.lt>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions