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| author |   Bard Liao <bardliao@realtek.com> | 2018-03-12 19:50:08 +0800 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2018-03-12 09:26:20 -0700 |
| commit | 3795e0c7d5c8b81d4ae32129b860aaa169945ce3 (patch) | |
| tree | ff89e47872193ef8e4dc01849131a4067bca65d4 /tools/perf/scripts/python/stackcollapse.py | |
| parent | ASoC: rt5659: fix wrong bit define for ADC L2 power. (diff) | |
| download | wireguard-linux-3795e0c7d5c8b81d4ae32129b860aaa169945ce3.tar.xz wireguard-linux-3795e0c7d5c8b81d4ae32129b860aaa169945ce3.zip | |
ASoC: rt5659: fix wrong control register for ADC2 power
The control register for ADC L2 and R2 is RT5659_PWR_DIG_1
not RT5659_PWR_DIG_2.
Signed-off-by: Zhong An <zhongan@pinecone.net>
Signed-off-by: Bard Liao <bardliao@realtek.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions