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| author |   Andre Przywara <andre.przywara@arm.com> | 2021-01-27 17:24:42 +0000 |
|---|---|---|
| committer |   Maxime Ripard <maxime@cerno.tech> | 2021-01-28 11:14:30 +0100 |
| commit | 394a36dd9dec7fd48b75dab23432632a30f241ea (patch) | |
| tree | 9591a885acd930a0298ff249a1021c121d1feede /tools/perf/scripts/python/stackcollapse.py | |
| parent | dt-bindings: clk: sunxi-ccu: Add compatible string for Allwinner H616 (diff) | |
| download | wireguard-linux-394a36dd9dec7fd48b75dab23432632a30f241ea.tar.xz wireguard-linux-394a36dd9dec7fd48b75dab23432632a30f241ea.zip | |
clk: sunxi-ng: Add support for the Allwinner H616 R-CCU
The clocks itself are identical to the H6 R-CCU, it's just that the H616
has not all of them implemented (or connected).
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20210127172500.13356-3-andre.przywara@arm.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions