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| author |   Michal Camacho Romero <michal.camacho.romero@intel.com> | 2026-01-14 13:39:10 +0100 |
|---|---|---|
| committer |   Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2026-01-15 18:17:50 +0100 |
| commit | 3b8907925a7964903955b59d974d98c7ae707d7a (patch) | |
| tree | 50811fa6c156efc13e615f551d26e3bcfcdc5df0 /tools/perf/scripts/python/stackcollapse.py | |
| parent | ACPICA: Logfile: Changes for version 20251212 (diff) | |
ACPICA: Replace TPRn Base and Limit registers
Replace TPRn Base and Limit registers with compatible bitmasks for them.
Link: https://github.com/acpica/acpica/commit/be91c5813936
Signed-off-by: Michal Camacho Romero <michal.camacho.romero@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Link: https://patch.msgid.link/1871109.TLkxdtWsSY@rafael.j.wysocki
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions