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| author |   Jagan Teki <jagan@amarulasolutions.com> | 2023-03-08 22:09:46 +0530 |
|---|---|---|
| committer |   Inki Dae <inki.dae@samsung.com> | 2023-03-28 09:05:40 +0900 |
| commit | 44d214a711d958b5c1f72e05f046f6b44a9766ea (patch) | |
| tree | 49f47951a8c68ba67197141c783c2b4519d87e14 /tools/perf/scripts/python/stackcollapse.py | |
| parent | drm: exynos: dsi: Add input_bus_flags (diff) | |
| download | wireguard-linux-44d214a711d958b5c1f72e05f046f6b44a9766ea.tar.xz wireguard-linux-44d214a711d958b5c1f72e05f046f6b44a9766ea.zip | |
drm: exynos: dsi: Add atomic_get_input_bus_fmts
Finding the right input bus format throughout the pipeline is hard
so add atomic_get_input_bus_fmts callback and initialize with the
proper input format from list of supported output formats.
This format can be used in pipeline for negotiating bus format between
the DSI-end of this bridge and the other component closer to pipeline
components.
List of Pixel formats are taken from,
AN13573 i.MX 8/RT MIPI DSI/CSI-2, Rev. 0, 21 March 2022
3.7.4 Pixel formats
Table 14. DSI pixel packing formats
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions