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| author |   Finley Xiao <finley.xiao@rock-chips.com> | 2018-12-29 14:33:13 +0100 |
|---|---|---|
| committer |   Heiko Stuebner <heiko@sntech.de> | 2019-01-07 09:17:15 +0100 |
| commit | 491b00ff699356a8dab10eb517a1b44205514c9e (patch) | |
| tree | be8f06d8817086217a331a4a356b1b753f1bd23b /tools/perf/scripts/python/stackcollapse.py | |
| parent | clk: rockchip: fix frac settings of GPLL clock for rk3328 (diff) | |
| download | wireguard-linux-491b00ff699356a8dab10eb517a1b44205514c9e.tar.xz wireguard-linux-491b00ff699356a8dab10eb517a1b44205514c9e.zip | |
clk: rockchip: add CLK_SET_RATE_PARENT for rk3066 lcdc dclks
Add CLK_SET_RATE_PARENT for both rk3066 lcdc dclk.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions