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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2022-11-21 17:13:42 +0100 |
|---|---|---|
| committer |   Thierry Reding <thierry.reding@gmail.com> | 2022-11-23 12:22:35 +0100 |
| commit | 50315945d178eebec4e8e2c50c265767ddb926eb (patch) | |
| tree | 307b0cf6e942f2801001c8f3f21492efbfaeeb64 /tools/perf/scripts/python/stackcollapse.py | |
| parent | dt-bindings: pwm: renesas,pwm-rcar: Add r8a779g0 support (diff) | |
| download | wireguard-linux-50315945d178eebec4e8e2c50c265767ddb926eb.tar.xz wireguard-linux-50315945d178eebec4e8e2c50c265767ddb926eb.zip | |
dt-bindings: pwm: renesas,tpu: Add r8a779g0 support
Document support for the 16-Bit Timer Pulse Unit (TPU) in the Renesas
R-Car V4H (R8A779G0) SoC.
Based on a patch in the BSP by CongDang.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions