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| author |   Duy Nguyen <duy.nguyen.rh@renesas.com> | 2024-02-01 15:19:17 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2024-02-22 11:03:32 +0100 |
| commit | 5db13ece46d6948d5c26429c2827a78ed3a5afc5 (patch) | |
| tree | e6c6a1b644b18870075514e2dd6e3ae6b9eaed99 /tools/perf/scripts/python/stackcollapse.py | |
| parent | arm64: dts: renesas: r8a779h0: Add L3 cache controller (diff) | |
| download | wireguard-linux-5db13ece46d6948d5c26429c2827a78ed3a5afc5.tar.xz wireguard-linux-5db13ece46d6948d5c26429c2827a78ed3a5afc5.zip | |
arm64: dts: renesas: r8a779h0: Add secondary CA76 CPU cores
Complete the description of the Cortex-A76 CPU cores and L3 cache
controllers on the Renesas R-Car V4M (R8A779H0) SoC, including CPU
topology and PSCI support for enabling CPU cores.
Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/c2a38a0da74915bf2a9171e53886c83a1c732934.1706796979.git.geert+renesas@glider.be
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
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