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author | 2023-06-06 12:35:03 +0300 | |
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committer | 2023-06-07 11:24:36 -0700 | |
commit | 626765bb4b2e732e9a1595fc801f696dbde12db9 (patch) | |
tree | 28428e6f788d3a6b020b530453422f1d49f92ec1 /tools/perf/scripts/python/stackcollapse.py | |
parent | drm/i915/dp: Fix log level for "CDS interlane align done" (diff) | |
download | wireguard-linux-626765bb4b2e732e9a1595fc801f696dbde12db9.tar.xz wireguard-linux-626765bb4b2e732e9a1595fc801f696dbde12db9.zip |
drm/i915: fix the derating percentage for MTL
Follow the values from bspec for the percentage overhead for
efficiency in MTL BW calculations.
Bspec: 64631
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230606093509.221709-2-vinod.govindapillai@intel.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions