diff options
| author |   Mika Kahola <mika.kahola@intel.com> | 2026-03-12 08:06:38 +0000 |
|---|---|---|
| committer | Mika Kahola <mika.kahola@intel.com> | 2026-03-24 09:45:49 +0200 |
| commit | 6e1c3b80ee801d1450a20a5420e79f9460bc5f0b (patch) | |
| tree | 2014863acd696b21fde48beaeb9d40a94f078399 /tools/perf/scripts/python/stackcollapse.py | |
| parent | drm/i915/lt_phy: Refactor LT PHY PLL handling to use explicit PLL state (diff) | |
drm/i915/lt_phy: Add lane_count to PLL state
Cache lane count as part of PLL state.
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20260312080657.2648265-6-mika.kahola@intel.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions