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| author |   Kan Liang <kan.liang@linux.intel.com> | 2021-04-12 07:31:02 -0700 |
|---|---|---|
| committer |   Peter Zijlstra <peterz@infradead.org> | 2021-04-19 20:03:29 +0200 |
| commit | 772ed05f3c5ce722b9de6c4c2dd87538a33fb8d3 (patch) | |
| tree | 82ea3c36c9ce8d14470171e8dfb52d5f38f2fca8 /tools/perf/scripts/python/stackcollapse.py | |
| parent | perf: Extend PERF_TYPE_HARDWARE and PERF_TYPE_HW_CACHE (diff) | |
| download | wireguard-linux-772ed05f3c5ce722b9de6c4c2dd87538a33fb8d3.tar.xz wireguard-linux-772ed05f3c5ce722b9de6c4c2dd87538a33fb8d3.zip | |
perf/x86/intel/uncore: Add Alder Lake support
The uncore subsystem for Alder Lake is similar to the previous Tiger
Lake.
The difference includes:
- New MSR addresses for global control, fixed counters, CBOX and ARB.
Add a new adl_uncore_msr_ops for uncore operations.
- Add a new threshold field for CBOX.
- New PCIIDs for IMC devices.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Link: https://lkml.kernel.org/r/1618237865-33448-23-git-send-email-kan.liang@linux.intel.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions