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| author |   Alain Volmat <avolmat@me.com> | 2021-03-31 22:42:17 +0200 |
|---|---|---|
| committer |   Patrice Chotard <patrice.chotard@foss.st.com> | 2021-08-06 09:30:01 +0200 |
| commit | 7c44e1515c84e394142c5e0c132b47af5d9142b8 (patch) | |
| tree | 4cfb2bbb3a637eb0b4e619ce57c61faa94c2d306 /tools/perf/scripts/python/stackcollapse.py | |
| parent | ARM: dts: sti: update flexgen compatible within stih418-clock (diff) | |
| download | wireguard-linux-7c44e1515c84e394142c5e0c132b47af5d9142b8.tar.xz wireguard-linux-7c44e1515c84e394142c5e0c132b47af5d9142b8.zip | |
ARM: dts: sti: update flexgen compatible within stih407-clock
With the introduction of new flexgen compatible within the clk-flexgen
driver, remove the clock-output-names entry from the flexgen nodes
and set the new proper compatible corresponding.
Signed-off-by: Alain Volmat <avolmat@me.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions