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| author |   Thierry Reding <treding@nvidia.com> | 2026-02-23 15:33:05 +0100 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2026-03-27 16:29:36 +0100 |
| commit | 8231b3dbd6c1343084cde94d38084f3b8160d1e1 (patch) | |
| tree | 0c76508e128a904fbd4334e3d14c898a2b37e557 /tools/perf/scripts/python/stackcollapse.py | |
| parent | arm64: tegra: Fix snps,blen properties (diff) | |
arm64: tegra: Drop redundant clock and reset names for TSEC
The DT bindings don't allow the clock and reset names to be specified
since there is only a single entry for each.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions