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| author |   Wesley Chalmers <Wesley.Chalmers@amd.com> | 2022-11-03 22:29:31 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2023-03-14 15:35:48 -0400 |
| commit | 825b3772a2047bd32ed3b3914234da0de19ef2e0 (patch) | |
| tree | 8b3cbde4c8598ce8c3ec00b364289befb8f280eb /tools/perf/scripts/python/stackcollapse.py | |
| parent | drm/amd/display: Take FEC Overhead into Timeslot Calculation (diff) | |
| download | wireguard-linux-825b3772a2047bd32ed3b3914234da0de19ef2e0.tar.xz wireguard-linux-825b3772a2047bd32ed3b3914234da0de19ef2e0.zip | |
drm/amd/display: Do not set DRR on pipe Commit
[WHY]
Writing to DRR registers such as OTG_V_TOTAL_MIN on the same frame as a
pipe commit can cause underflow.
Cc: stable@vger.kernel.org
Cc: Mario Limonciello <mario.limonciello@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions