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| author |   Andreas Schwab <schwab@suse.de> | 2019-05-07 09:36:46 +0200 |
|---|---|---|
| committer |   Palmer Dabbelt <palmer@sifive.com> | 2019-05-16 20:42:13 -0700 |
| commit | 8fef9900d43feb9d5017c72840966733085e3e82 (patch) | |
| tree | 6343590c54c1b8c5e1d74f83e0da13d1d7e0a92f /tools/perf/scripts/python/stackcollapse.py | |
| parent | RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs (diff) | |
| download | wireguard-linux-8fef9900d43feb9d5017c72840966733085e3e82.tar.xz wireguard-linux-8fef9900d43feb9d5017c72840966733085e3e82.zip | |
riscv: fix locking violation in page fault handler
When a user mode process accesses an address in the vmalloc area
do_page_fault tries to unlock the mmap semaphore when it isn't locked.
Signed-off-by: Andreas Schwab <schwab@suse.de>
[Palmer: Duplicated code instead of a goto]
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions