diff options
| author |   John Crispin <john@phrozen.org> | 2026-03-11 19:39:38 +0100 |
|---|---|---|
| committer |   Bjorn Andersson <andersson@kernel.org> | 2026-03-30 09:02:11 -0500 |
| commit | a57666004f49fa5031d6bf388834213e6f961922 (patch) | |
| tree | 68751678a4d49e7aaf2314e05bcf504e40cacdb5 /tools/perf/scripts/python/stackcollapse.py | |
| parent | clk: qcom: gdsc: Fix error path on registration of multiple pm subdomains (diff) | |
dt-bindings: clock: qcom: Add CMN PLL support for IPQ6018
The CMN PLL block in the IPQ6018 SoC takes 48 MHz as the reference
input clock. Its output clocks are the bias_pll_cc_clk (300 MHz) and
bias_pll_nss_noc_clk (416.5 MHz) clocks used by the networking
subsystem.
Add the related compatible for IPQ6018 to the ipq9574-cmn-pll
generic schema.
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260311183942.10134-2-ansuelsmth@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions