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| author |   Bartosz Wawrzyniak <bwawrzyn@cisco.com> | 2023-03-16 10:03:39 +0000 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2023-03-19 08:39:21 +0000 |
| commit | b31587feaa0133b19a1900a26bce07a3c6d21af6 (patch) | |
| tree | c4949401f178536981907560e73a01aa58b6a347 /tools/perf/scripts/python/stackcollapse.py | |
| parent | Merge branch 'net-better-const' (diff) | |
| download | wireguard-linux-b31587feaa0133b19a1900a26bce07a3c6d21af6.tar.xz wireguard-linux-b31587feaa0133b19a1900a26bce07a3c6d21af6.zip | |
net: macb: Set MDIO clock divisor for pclk higher than 160MHz
Currently macb sets clock divisor for pclk up to 160 MHz.
Function gem_mdc_clk_div was updated to enable divisor
for higher values of pclk.
Signed-off-by: Bartosz Wawrzyniak <bwawrzyn@cisco.com>
Reviewed-by: Michal Kubiak <michal.kubiak@intel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions