diff options
| author |   Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> | 2026-01-15 06:08:08 +0000 |
|---|---|---|
| committer |   Joerg Roedel <joerg.roedel@amd.com> | 2026-01-18 10:56:12 +0100 |
| commit | b43a29def24f38a28085635e2be39566671976a8 (patch) | |
| tree | ec4722eeb568b80b8f322cfc4b513d4e7ff91f0e /tools/perf/scripts/python/stackcollapse.py | |
| parent | iommu/amd: Always enable GCR3TRPMode when supported. (diff) | |
iommu/amd: Add support for nest parent domain allocation
To support nested translation, the nest parent domain is allocated with
IOMMU_HWPT_ALLOC_NEST_PARENT flag, and stores information of the v1 page
table for stage 2 (i.e. GPA->SPA).
Also, only support nest parent domain on AMD system, which can support
the Guest CR3 Table (GCR3TRPMode) feature. This feature is required in
order to program DTE[GCR3 Table Root Pointer] with the GPA.
Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions