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author | 2021-02-14 11:10:55 -0800 | |
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committer | 2021-02-14 11:10:55 -0800 | |
commit | c553021498640050340924bd62fa580e253467ac (patch) | |
tree | 77351d0100c901ec41e2cdcd3e8e058b6645e738 /tools/perf/scripts/python/stackcollapse.py | |
parent | Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux (diff) | |
parent | x86/pci: Create PCI/MSI irqdomain after x86_init.pci.arch_init() (diff) | |
download | wireguard-linux-c553021498640050340924bd62fa580e253467ac.tar.xz wireguard-linux-c553021498640050340924bd62fa580e253467ac.zip |
Merge tag 'x86_urgent_for_v5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 fixes from Borislav Petkov:
"I kinda knew while typing 'I hope this is the last batch of x86/urgent
updates' last week, Murphy was reading too and uttered 'Hold my
beer!'.
So here's more fixes... Thanks Murphy.
Anyway, three more x86/urgent fixes for 5.11 final. We should be
finally ready (famous last words). :-)
- An SGX use after free fix
- A fix for the fix to disable CET instrumentation generation for
kernel code. We forgot 32-bit, which we seem to do very often
nowadays
- A Xen PV fix to irqdomain init ordering"
* tag 'x86_urgent_for_v5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/pci: Create PCI/MSI irqdomain after x86_init.pci.arch_init()
x86/build: Disable CET instrumentation in the kernel for 32-bit too
x86/sgx: Maintain encl->refcount for each encl->mm_list entry
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
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