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| author |   Wolfram Sang <wsa+renesas@sang-engineering.com> | 2021-01-21 11:06:16 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2021-01-25 09:46:22 +0100 |
| commit | c5e91ba25a65378edb013fbfe418b65d74f9aae5 (patch) | |
| tree | a8124f9832cada3f1b5a068e5ed4b6867295689d /tools/perf/scripts/python/stackcollapse.py | |
| parent | clk: renesas: r8a779a0: Add I2C clocks (diff) | |
| download | wireguard-linux-c5e91ba25a65378edb013fbfe418b65d74f9aae5.tar.xz wireguard-linux-c5e91ba25a65378edb013fbfe418b65d74f9aae5.zip | |
clk: renesas: r8a779a0: Add RAVB clocks
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210121100619.5653-3-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions