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| author |   Dan Williams <dan.j.williams@intel.com> | 2023-06-14 18:30:19 -0700 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2023-06-25 14:31:08 -0700 |
| commit | cecbb5da921231aa0933667fba85bea5b91d6a46 (patch) | |
| tree | e3deff60d39b18a84b4bb494eaacf04c6275f50e /tools/perf/scripts/python/stackcollapse.py | |
| parent | cxl/port: Rename CXL_DECODER_{EXPANDER, ACCELERATOR} => {HOSTONLYMEM, DEVMEM} (diff) | |
| download | wireguard-linux-cecbb5da921231aa0933667fba85bea5b91d6a46.tar.xz wireguard-linux-cecbb5da921231aa0933667fba85bea5b91d6a46.zip | |
cxl/hdm: Default CXL_DEVTYPE_DEVMEM decoders to CXL_DECODER_DEVMEM
In preparation for device-memory region creation, arrange for decoders
of CXL_DEVTYPE_DEVMEM memdevs to default to CXL_DECODER_DEVMEM for their
target type.
Revisit this if a device ever shows up that wants to offer mixed HDM-H
(Host-Only Memory) and HDM-DB support, or an CXL_DEVTYPE_DEVMEM device
that supports HDM-H.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/168679261945.3436160.11673393474107374595.stgit@dwillia2-xfh.jf.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions