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| author |   Thomas Gleixner <tglx@linutronix.de> | 2017-09-21 11:57:08 +0200 |
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| committer | Thomas Gleixner <tglx@linutronix.de> | 2017-09-21 11:57:08 +0200 |
| commit | cf00ab842eec7cd4923a3f0f3b5ddcead9b11306 (patch) | |
| tree | 07ed14114821cd8eadf3ecde2a1cbaea045bf85d /tools/perf/scripts/python/stackcollapse.py | |
| parent | Revert "genirq: Restrict effective affinity to interrupts actually using it" (diff) | |
| parent | irqchip.mips-gic: Fix shared interrupt mask writes (diff) | |
| download | wireguard-linux-cf00ab842eec7cd4923a3f0f3b5ddcead9b11306.tar.xz wireguard-linux-cf00ab842eec7cd4923a3f0f3b5ddcead9b11306.zip | |
Merge tag 'irqchip-4.14-2' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/urgent
Pull irqchip updates from Marc Zyngier
- A GICv3 initialisation fix when some CPUs fail to be brought up
- A GICv4 compile fix for GCC 4.5 (!)
- A MIPS-GIC fix for the PCIe support
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
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