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| author |   Tudor Ambarus <tudor.ambarus@linaro.org> | 2024-01-19 11:11:30 +0000 |
|---|---|---|
| committer |   Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2024-01-23 13:53:19 +0100 |
| commit | d97b6c902a40673debee3cb98d79405193890f34 (patch) | |
| tree | 87fd03a5f04c571439c0bd55dd6508b8ca06a61a /tools/perf/scripts/python/stackcollapse.py | |
| parent | arm64: dts: exynos: gs101: enable cmu-peric0 clock controller (diff) | |
| download | wireguard-linux-d97b6c902a40673debee3cb98d79405193890f34.tar.xz wireguard-linux-d97b6c902a40673debee3cb98d79405193890f34.zip | |
arm64: dts: exynos: gs101: update USI UART to use peric0 clocks
Get rid of the dummy clock and start using the cmu_peric0 clocks
for the usi_uart and serial_0 nodes.
Tested the serial at 115200, 1000000 and 3000000 baudrates,
everthing went fine.
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Link: https://lore.kernel.org/r/20240119111132.1290455-7-tudor.ambarus@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions