diff options
| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2025-10-14 10:50:20 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-10-14 10:50:20 +0200 |
| commit | daa5a9bc67f31b77649d885cf5f64d542c0524fd (patch) | |
| tree | 509b76d68ec09a0c9eb92a33ac7b04cdb82ad7f2 /tools/perf/scripts/python/stackcollapse.py | |
| parent | clk: renesas: Use IS_ERR() for pointers that cannot be NULL (diff) | |
| parent | dt-bindings: clock: renesas,r9a09g047-cpg: Add USB2 PHY core clocks (diff) | |
Merge tag 'renesas-r9a09g047-dt-binding-defs-tag5' into renesas-clk-for-v6.19
Renesas RZ/G3E USB2 PHY Core Clock DT Binding Definitions
USB2 PHY core clock DT binding definitions for the Renesas RZ/G3E
(R9A09G047) SoC, shared by driver and DT source files.
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions