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| author |   Tony Lindgren <tony@atomide.com> | 2024-03-27 09:10:37 +0200 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2024-04-10 09:15:38 +0300 |
| commit | de36994d7639024cde1f7d1dd6d9d69e7243572f (patch) | |
| tree | 66d51c4c726eee9c7cc2a976e4d6691a275980f3 /tools/perf/scripts/python/stackcollapse.py | |
| parent | ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_CORE (diff) | |
| download | wireguard-linux-de36994d7639024cde1f7d1dd6d9d69e7243572f.tar.xz wireguard-linux-de36994d7639024cde1f7d1dd6d9d69e7243572f.zip | |
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_DSP
With the clkcsel binding we can drop the custom ti,bit-shift devicetree
property in favor of the standard reg property and reduce the number of
clocks to update for the make W-1 dtbs warnings.
Let's also add a comment for the clocksel clock that matches the
documentation.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions