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| author |   Davidlohr Bueso <dave@stgolabs.net> | 2022-12-15 10:38:36 -0800 |
|---|---|---|
| committer |   Dan Williams <dan.j.williams@intel.com> | 2023-01-05 15:01:45 -0800 |
| commit | e520d52d7cabf6817b2c56d2681e9618bc5540ae (patch) | |
| tree | 0e1dc26bf122f21c5b8206263e4b7b32fb7a01fc /tools/perf/scripts/python/stackcollapse.py | |
| parent | PCI/CXL: Export native CXL error reporting control (diff) | |
| download | wireguard-linux-e520d52d7cabf6817b2c56d2681e9618bc5540ae.tar.xz wireguard-linux-e520d52d7cabf6817b2c56d2681e9618bc5540ae.zip | |
cxl/region: Only warn about cpu_cache_invalidate_memregion() once
No need for more than once per module load.
Signed-off-by: Davidlohr Bueso <dave@stgolabs.net>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/20221215183836.24136-1-dave@stgolabs.net
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions