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| author |   Jerome Brunet <jbrunet@baylibre.com> | 2018-10-29 16:13:39 +0100 |
|---|---|---|
| committer |   Linus Walleij <linus.walleij@linaro.org> | 2018-11-05 09:33:22 +0100 |
| commit | e91b162d2868672d06010f34aa83d408db13d3c6 (patch) | |
| tree | 24e14bb7887b31b36d84fb204b9f1f08e5ffcde2 /tools/perf/scripts/python/stackcollapse.py | |
| parent | pinctrl: meson: fix gxl ao pull register bits (diff) | |
| download | wireguard-linux-e91b162d2868672d06010f34aa83d408db13d3c6.tar.xz wireguard-linux-e91b162d2868672d06010f34aa83d408db13d3c6.zip | |
pinctrl: meson: fix meson8 ao pull register bits
AO pull register definition is inverted between pull (up/down) and
pull enable. Fixing this allows to properly apply bias setting
through pinconf
Fixes: 6ac730951104 ("pinctrl: add driver for Amlogic Meson SoCs")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions