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| author |   Ovidiu Panait <ovidiu.panait.rb@renesas.com> | 2025-12-09 09:11:14 +0000 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2025-12-29 11:43:22 +0100 |
| commit | ebb3acf4d7c95b52265084168b59a565bf972883 (patch) | |
| tree | 41c1257cfe9a02b18eb55ec0a96f3f3142be8c6c /tools/perf/scripts/python/stackcollapse.py | |
| parent | clk: renesas: r9a09g057: Add entries for RSCIs (diff) | |
clk: renesas: r9a09g056: Add clock and reset entries for TSU
Add module clock and reset entries for the TSU0 and TSU1 blocks on the
Renesas RZ/V2N (R9A09G056) SoC.
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251209091115.8541-3-ovidiu.panait.rb@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions