diff options
| author |   Krishna Manikandan <mkrishn@codeaurora.org> | 2020-03-20 18:41:04 +0530 |
|---|---|---|
| committer |   Bjorn Andersson <bjorn.andersson@linaro.org> | 2020-04-13 22:05:02 -0700 |
| commit | eccdac07ae300bbe31ab4230a5ac522c1044d0e1 (patch) | |
| tree | b8fbb8bf82de993395eacc87028f84b3c77902b2 /tools/perf/scripts/python/stackcollapse.py | |
| parent | arm64: dts: qcom: sc7180: Include interconnect definitions (diff) | |
| download | wireguard-linux-eccdac07ae300bbe31ab4230a5ac522c1044d0e1.tar.xz wireguard-linux-eccdac07ae300bbe31ab4230a5ac522c1044d0e1.zip | |
arm64: dts: qcom: sc7180: modify assigned clocks for sc7180 target
Add DISP_CC_MDSS_ROT_CLK and DISP_CC_MDSS_AHB_CLK
in the assigned clocks list as these are display
specific clocks and needs to be initialized from
the client side. Adding the default rate of
19.2 mhz for these clocks for sc7180 target.
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
Link: https://lore.kernel.org/r/1584709864-5587-1-git-send-email-mkrishn@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions