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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2025-12-15 11:48:57 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-12-15 11:48:57 +0100 |
| commit | eede457b4c823d183e1c95d7286ca08614baa36a (patch) | |
| tree | e57b2a679d605bd527331e3d11b768bba6fdcdf3 /tools/perf/scripts/python/stackcollapse.py | |
| parent | clk: renesas: rzg2l: Select correct div round macro (diff) | |
| parent | dt-bindings: clock: renesas,r9a09g077/87: Add XSPI0/1 IDs (diff) | |
Merge tag 'renesas-r9a09g077-dt-binding-defs-tag5' into renesas-clk-for-v6.20
Renesas RZ/T2H and RZ/N2H XSPI Clock DT Binding Definitions
XSPI Clock DT binding definitions for the Renesas RZ/T2H (R9A09G077) and
RZ/N2H (R9A09G087) SoCs, shared by driver and DT source files.
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions