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| author |   Masahiro Yamada <yamada.masahiro@socionext.com> | 2017-10-13 21:54:46 +0900 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@codeaurora.org> | 2017-10-24 01:57:24 -0700 |
| commit | db9d79f6e7de3e059d897234f93cbe1e55a0ed50 (patch) | |
| tree | dbc0de52d0bc6ad461f3a294374bbcda06c5faa8 /tools/perf/scripts/python/stat-cpi.py | |
| parent | clk: samsung: exynos4: Enable VPLL and EPLL clocks for suspend/resume cycle (diff) | |
| download | wireguard-linux-db9d79f6e7de3e059d897234f93cbe1e55a0ed50.tar.xz wireguard-linux-db9d79f6e7de3e059d897234f93cbe1e55a0ed50.zip | |
clk: uniphier: fix clock data for PXs3
Fix reg offsets of USB clocks.
Fixes: 736de651a836 ("clk: uniphier: add PXs3 clock data")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'tools/perf/scripts/python/stat-cpi.py')
0 files changed, 0 insertions, 0 deletions