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| author |   Russell King - ARM Linux <linux@arm.linux.org.uk> | 2011-07-21 17:13:48 +0100 |
|---|---|---|
| committer |   Vinod Koul <vinod.koul@intel.com> | 2011-07-26 15:33:29 +0530 |
| commit | 121c8476a3c39a483326c33526e72a07661df1fc (patch) | |
| tree | e0cdeae942aebffac59c4c375bc7eef9f0f549dc /tools/perf/scripts/python/syscall-counts-by-pid.py | |
| parent | DMA: PL08x: cleanup selection of buswidth (diff) | |
| download | wireguard-linux-121c8476a3c39a483326c33526e72a07661df1fc.tar.xz wireguard-linux-121c8476a3c39a483326c33526e72a07661df1fc.zip | |
DMA: PL08x: avoid recalculating cctl at each prepare
Now that we have separate cctl values for M>P and P>M transfers, we can
avoid calculating the cctl value each time we prepare a transaction.
Move the bus selection and increment setting to the slave configuration
and initialization functions.
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts-by-pid.py')
0 files changed, 0 insertions, 0 deletions