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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2022-11-15 09:34:14 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-11-16 09:05:59 +0100 |
| commit | 777bcc85e1fbadfea1927e828165102cf5050b53 (patch) | |
| tree | 4a7d33363ca6ff1d3421c2077435c599bfa47d5b /tools/perf/scripts/python/syscall-counts-by-pid.py | |
| parent | clk: renesas: r8a779g0: Add Z0 clock support (diff) | |
| download | wireguard-linux-777bcc85e1fbadfea1927e828165102cf5050b53.tar.xz wireguard-linux-777bcc85e1fbadfea1927e828165102cf5050b53.zip | |
clk: renesas: r8a779f0: Fix Ethernet Switch clocks
The RSwitch2 and EtherTSN-IF clocks were accidentally mixed up.
While at it, rename them to better match the (future) documentation.
Fixes: a3b4137a4d4023e6 ("clk: renesas: r8a779f0: Add Ethernet Switch clocks")
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/99b8b41bd2c5043c9e457862ef4bc144869eca58.1668501212.git.geert+renesas@glider.be
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts-by-pid.py')
0 files changed, 0 insertions, 0 deletions