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| author |   Heiner Kallweit <hkallweit1@gmail.com> | 2022-08-14 23:25:31 +0200 |
|---|---|---|
| committer |   Jerome Brunet <jbrunet@baylibre.com> | 2022-11-08 17:05:02 +0100 |
| commit | d73406ed2dcfab7d25493ff3a62dd57f0d9c2bf2 (patch) | |
| tree | 79ee0e88858d7c3784e8fe6bd1982827fdfd3622 /tools/perf/scripts/python/syscall-counts-by-pid.py | |
| parent | clk: meson: pll: adjust timeout in meson_clk_pll_wait_lock() (diff) | |
| download | wireguard-linux-d73406ed2dcfab7d25493ff3a62dd57f0d9c2bf2.tar.xz wireguard-linux-d73406ed2dcfab7d25493ff3a62dd57f0d9c2bf2.zip | |
clk: meson: pll: add pcie lock retry workaround
The PCIe PLL locking may be unreliable under some circumstance, such as
high or low temperature. If the PLL fails to lock, reset it a try again.
This helps on the S905X4
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
[commit message amend]
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/cc80cda0-4dda-2e3e-3fc8-afa97717479b@gmail.com
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts-by-pid.py')
0 files changed, 0 insertions, 0 deletions