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| author |   Yifan Zhang <yifan1.zhang@amd.com> | 2024-05-23 14:10:30 +0800 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2024-06-05 11:02:37 -0400 |
| commit | 301dfbfc84e81f2ee80a84574432df52125d2b4a (patch) | |
| tree | c49c5fed1101186a3d6535458fcaf96e59b609c3 /tools/perf/scripts/python/syscall-counts.py | |
| parent | drm/amdgpu: init SAW registers for mmhub v3.3 (diff) | |
| download | wireguard-linux-301dfbfc84e81f2ee80a84574432df52125d2b4a.tar.xz wireguard-linux-301dfbfc84e81f2ee80a84574432df52125d2b4a.zip | |
drm/amdgpu: disable lane0 L1TLB and enable lane1 L1TLB
This patch to disable lane0 L1TLB and enable lane1 L1TLB.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions